In semiconductor manufacturing technology, there is pressure to increase a real density and manufacturing speed and simultaneously to reduce manufacturing cost. The scaling of semiconductor devices on integrated circuit (IC) chips, and Complementary Metal Oxide Semiconductor (CMOS) transistor devices in particular, is reaching into the sub-micrometer region, generally following Moore's law. The number of devices integrated into an IC chip is of the order of tens of millions and increasing. Interconnection of signals between these devices now involves many layers of metal interconnections separated from each either by dielectric materials. Eight interconnection layers are usual at present. However, the number of layers is expected to increase. As IC dimensions reduce, RC time constants associated with resistance in and parasitic capacitance between the interconnections increase. This is because spacing between ground planes and signal lines reduces and the resistance of the signal lines increases. These effects limit switching speed in the IC.
In conventional ICs, the interconnects are formed from Aluminium typically by subtractive reactive ion etching. In more recent IC designs, the interconnects are formed from Copper. Copper provides less resistance than Aluminum and increased reliability. However, Copper interconnects cannot be formed easily by subtractive reactive ion etching. Instead, Copper interconnects are typically formed via a process called Dual Damascene. In the Dual Damascene process, a cylindrical hole is etched in an inter-layer dielectric (ILD), followed by a trench. The hole and trench are then filled with copper. The copper filling is then polished back by a chemical mechanical polishing (CMP) operation. This produces a copper via connection extending orthogonally from a lateral, inlaid copper signal line.
In detail, Dual Damascene usually involves deposition on a substrate of a first silicon nitride layer, a first layer of dielectric on the first silicon nitride layer, a second silicon nitride etch stop layer on the first dielectric layer, a second dielectric layer on the second silicon nitride layer, and a final hard mask layer. The substrate is then coated with photo resist and lithographically patterned. The ILD electrical properties are the average of the two dielectric layers and the two silicon nitride layers. An anisotropic dry etch cuts through the final layer and the two dielectric layers, stopping on the first silicon nitride layer. The photo resist is then stripped to leave a via in the ILD layer. The hard mask layer protects the ILD from the photo resist stripping process. Photo resist is again applied to the substrate and lithographically patterned. A trench etch then cuts through the ILD to the etch stop layer. The first silicon nitride layer is then opened by another etch. The photo resist is stripped. A tantalum barrier is deposited to line the hole/trench structure. The barrier prevents copper from diffusing into the ILD. A copper seed layer is then deposited using PVD. Bulk Copper is then deposited by electroplating. The copper deposition is polished back by CMP to the top of the trench. This process may be repeated to build up additional interconnection layers.
A disadvantage with Dual Damascene is that, during the second application of resist, usually by spinning, resist material pools in the vias. This creates local regions of extra thick resist on areas in which the vias are to be patterned. Additionally, because the features to be etched are relatively deep, it is difficult to achieve depths of focus desired for efficient photolithography. Economically, the relatively large number of steps involved make Dual Damascene very expensive to perform.
Parasitic capacitance between interconnects can be reduced by forming the dielectric layers from low-k dielectric materials. SiLK (trade mark of the Dow Chemical Company) is one well-known example of such a material. However, such low-k dielectric materials are not compatible with Dual Damascene. This is because low k dielectrics are in general susceptible to the same chemical processes that strip resist in Dual Damascene.
Another conventional technique for shaping materials on a substrate is Ultra Violet (UV) imprint lithography or UV molding. Referring to FIG. 1, in UV imprint lithography, a layer of a low viscosity pre-polymer liquid resist 110 is applied to a substrate 100. At step 2, a transparent patterned stamp 120 is pressed into the resist 110. The resist 110 is exposed to UV through the stamp 120. The exposed resist 110 cures and hardens. At step 3, the stamp 120 is removed from the patterned solidified resist 110. The substrate 100 is then peeled to leave the hardened resist 110 with thicker and thinner zones corresponding to the pattern of the stamp 120. The imprint in the resist layer 110 is substantially a replica of the pattern on the stamp 120. See, for example, M. Colburn et al. “Patterning non-flat substrates with a low pressure, room temperature imprint process”, J. Vac. Sci. Technol. B. 6, 2161 (2001). UV imprint lithography permits molding of polymer features with a relatively high aspect ratio and vertical side walls. Alignment between the stamp 120 and the substrate 100 can be achieved optically through the stamp. See, for example, Choi et al, “Layer-to-layer alignment for step and flash imprint lithography”, SPIE, 2001; White and Wood, “Novel alignment system for imprint lithography”, J. Vac. Sci. Technol. 18, 3552, 2000). UV imprint lithography may also be performed with an elastomeric stamp. See, for example, Bietsch and Michel, “Conformal contact and pattern stability of stamps used for soft lithography”, J. Appl. Phys. 88, 4310 (2000); Johnson, Contact Mechanics, Cambridge University Press, Cambridge (1985); and S. P. Timoshenko and J. N. Goodier, Theory of Elasticity, Mc-Graw-Hill, New York.
However, it is difficult to fully displace the resist on relatively large areas to achieve a pattern with satisfactory contrast. There is usually a residual layer left. Calculations for displacement of liquids can be derived from lubrication theory. See, for example A. Cameron, Basic Lubrication Theory Wiley, New York (1981). Relatively thin residual layers can be trivially removed by ashing. Ashing can remove a defined layer of polymer from both the protruding and depressed zones. Ashing provides access to the substrate in desired zones to create a binary contrast similar to that conventionally provided by resist patterning.